This invention relates to electronic computer systems and the like, and more particularly relates to improved methods and apparatus for achieving a video display having high resolution.
Related U.S. patent applications are: application Ser. No. 633,384 entitled "Single Chip DRAM Controller and CRT Controller" by Robert C. Thaden and Jeffery C. Bond, application Ser. No. 633,386 entitled "Video Memory Controller" by Robert C. Thaden, Jeffery C. Bond, James C. Moravec, Karl M. Guttag, Raymond Pinkham and Mark Novak, application Ser. No. 633,367 entitled "State Machine Standard Cell" by Robert C. Thaden and Mark W. Watts, application Ser. No. 633,389 entitled "X Y Addressing" by Karl M. Guttag, Jerry Van Aken, Jeffery C. Bond, Rudy Albachten and Mark Novak, application Ser. No. 633,383 entitled "Video System with Single Memory Space for Instructions, Program Data and Display Data" by Karl M. Guttag, Raymond Pinkham and Mark Novak, application Ser. No. 633,388 entitled "Single Chip Video System with Separate Clocks for Memory Controller and CRT Controller" by Robert C. Thaden and Jeffery C. Bond and application Ser. No. 633,387 entitled "Video Memory Controller Support Storage of Data From an External Source" by Jeffery C. Bond and Robert C. Thaden.
It is conventional to present the output from a computer as an image on the screen of a cathode ray tube or the like. The screen is actually composed of a collection of dots or "pixels", and the image is therefore produced by selecting and illuminating those pixels necessary to form the desired image. If the image sought to be presented is merely a simplistic pattern of numbers or other symbols, this may be achieved with a relatively limited number of pixels. However, if a more complex image (with a greater resolution) is desired, then a screen must be chosen which has a substantially greater number of pixels.
It should be understood that each pixel used to form the image is illuminated by a separate output data signal from the processing section of the computer, and that an increase in resolution requires a screen having a greater number of pixels. More particularly, since each video data signal must also be stored before being transferred to the video screen, an increase in image resolution also requires that the data storage section have a corresponding increase in the number of memory cells for receiving and holding all of these data signals.
If a different screen having an increased number of pixels is employed for the purpose of enhancing the resolution of the image displayed on the screen, this will not by itself cause a disproportionate increase in the overall cost of the system. However, the size or capacity of the memory component or circuit is a significant factor in the cost of the system, and an increase in the resolution of the image being presented effectively decreases the time interval available to effect a complete transfer of all of the data signals between the storage and the video section.
There have been many attempts and proposals for overcoming or mitigating these disadvantages. In particular, a larger storage unit may be selected to accommodate the increased number of input signals, but as hereinbefore explained, such a unit is inherently expensive, and its use in home computer systems will disproportionately increase the costs of such computer systems. The technology is available to provide specially designed memory units capable of fast access for higher data velocity, but such units are even more expensive than slower access memory units.
Alternatively, an increase in data storage capacity may be achieved by simply adding additional memory units. However, this not only increases the overall cost of the system, since each memory unit is a separate storage component this tends to increase the length of the time required to transfer video data to the pixels.
It has been proposed to mitigate part of the problem which arises when the data storage is composed of a plurality of separate random-access memory units or "chips", by interconnecting them in parallel with a shift register, whereby all of the units may be unloaded and their contents transferred to the shift register at the same time. The data in the shift register is then sequentially clocked to the pixels at the proper video data rate. Although this technique has been extremely beneficial in reducing the data transfer cycle to that corresponding to a single memory chip, it does not attack the problem of increased cost. Moreover, since the storage circuit is composed of memory units of standard design, there will inherently be more cells in the storage unit than there are pixels on the video screen, and whenever the storage is unloaded into the video section, it is necessary to unload more cells than are actually required to produce the image.
The control circuits for the prior art systems required three different controllers, one for handling system memory, one for handling of text information and one for handling of graphic information. These systems often resulted in bottlenecks at the video memory.
The text subsystem is only required if the performance of the bit-mapped controller subsystem is insufficient to handle text in a reasonable period of time. Today in a number of products, the text and graphics are combined into one subsystem. These systems, however, have the drawback that they must have physically separate data buses between the least part of the system memory and the display memory. In one example--part of the main system memory is in a shared memory space with the display data, there is a separate isolated data bus that connects to a high speed ROM that is used to contain important (for performance) routines.
Due to the fact that most display devices must be constantly refreshed with display data, there is a need for a relatively constant "background" task that continually transfers the contents of the display memory to the display device. This "background" with normal RAMs can monopolize the data bus into and out of the RAMs for as much as 85% (percent). With the multiport video RAM type device (such as Texas Instrument Inc's TMS4161 for example), the amount of data bus requirement needed for the display refresh task can be dropped down to less than 3%. On the other hand, the aforementioned bottleneck created when other types of RAMs are used.
In systems using conventional memories for holding the display data it is imperative that the significant portion of the processor's main system memory not be on the same physical data bus as the display data bus, or else the system performance would be substantially reduced. For example if the processor were connected on a bus where 80% of the bus cycles were allocated to display refresh, the overall system performance could be degraded by as much as 5 times (due to only getting 20% or 1/5th of the accesses).
The solutions to date, using conventional memories for the display data, have been to isolate at least a significant portion (if not all) the CPU's main system memory data bus from the display memory data bus. This isolation lets the processor run significantly faster on the isolated system memory bus that it can out of the display memory bus. In some cases, such as systems using a NEC7220 manufactured by Nippon Electric Corporation, the isolation of the display memory is such that the processor has only very limited access to the display memories.
Prior art video system controllers required that data be written to one bank of memories in a single memory cycle. Therefore, to draw an object requires writing to each bank of memory or each color plane individually. An example of this is provided in a device NEC 7220 manufactured by Nippon Electric Corporation.
A video system is able to change the display on a video monitor with a minimal number of memory transfer cycles. The video system includes a monitor for displaying of processed data, a processor means for processing the data to be displayed, a display memory means divided into a plurality of planes addressable by a row address, the display memory stores the data that has been processed by the processor means. There are additional other sources of data which is processed by the processor means for storing in the display memory and subsequently being displayed by the CRT monitor. A control means controls the data transfer between the data sources, the processor, the display memories, and the CRT monitor and includes a row address override circuit. The row address override circuit comprises a plurality of output logic for providing a write enable signal to a memory plane. Each memory plane is connected to a corresponding output logic circuit. A select means selects a source of data that is to be written to the memory plane, and an override means provides a write enable to a preselected number of memory planes simultaneously with the same predetermined number of output logic circuits.
The row address select override circuit allows writing data to memory N times faster than without this mode, N being the number of memory planes within the system. In the video system controller discussed, four row address select planes are supported. In one embodiment, each of the four planes represents a color plane. Writing to one plane generates an image in one primary color. Writing the same data to two planes generates a mixed color. Using the override feature allows writing to both planes at the same time. This feature also provides for faster clearing of the screen being all four planes may be written to in a single transfer cycle to provide a row address select blank function.
The video memory and CRT controller or video system controller (VSC) controls two essential features.
1. Normal Dynamic Ram control--This may include all or part of the following--DRAM refresh address generation, RAS and CAS strobes, write enable generation, row and column address multiplexing, and other features found in standard dynamic ram controllers. A CPU or other Host processor is given direct or indirect access to the Dynamic RAM.
2. The special generation necessary to effect the transfer of the to and/or from the memory array and the shift register inside the special VRAMs.
Further significant features that may be included are:
2A. The control hardware necessary to cause the transfer to or from the memory array and the shift register inside the memory array to happen automatically. This hardware may be in the form of programmable or fixed counters that once initialized will cause the transfers to be made automatically in a relationship that is related to the vertical and horizontal scanning of a display device such as a CRT.
3. Including a timing function (either programmable or fixed timing) that produces control signal outputs necessary for the control of a display device like (but not limited to) a CRT.
4. Since there may be multiple operations needing to access the bus such as the host processor access, DRAM refresh, and shift register transfers, it is generally preferred that arbitration logic that controls which of conflicting requests gets the bus, and then sees that the appropriate address is applied to the addresses of the memories is included. This may involve including internal or external address multiplexing.
4A. In the case where host processor conflict with DRAM refresh or other accesses it may be desirable to indicate that the cycle of the host needs to be extended by the means of a "not-ready" like signal.
5. Signals from a host processor may directly/asynchronously effect the address, RAS, CAS DRAM timing or the timing could be controlled synchronously to the controller after the request signals from the host have been synchronized. Or there could be a mixture of synchronous and asynchronous control where normally the host directly controls the DRAM control signal except in cases where there is an access conflict where the controller detects this conflict and substitutes its own control signals and indicates a longer request cycle.
6. In addition to controlling special VRAM, the video controller may also control standard dynamic RAM's.
These and other features/advantages may be apparent from a reading of the specification in conjunction with the figures in which: